Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies

COMMERCIAL DESIGNS currently integrate tens to hundreds of embedded functional and storage blocks in a monolithic SoC, and the number is expected to increase significantly in the near future. Specifically, molecular-scale computing will allow additional orders-of-magnitude improvements in device density. The possibility of such high levels of integration in a single chip necessitates the design of high-bandwidth, low-power interconnect architectures. With the well-known trend of continued CMOS scaling in accordance with Moore’s law, it’s projected that traditional on-chip interconnect systems will soon be very limited in meeting the performance needs and specifications of ICs and SoCs. This limit stems primarily from global interconnect delays which significantly exceed gate delays. Copper and low-k dielectrics have been introduced to decrease the global interconnect delay, but these traditional materials extend the lifetime of conventional interconnect systems only by a few technology generations. According to the International Technology Roadmap for Semiconductors (ITRS), material innovation with traditional scaling will no longer satisfy performance requirements over the long term, which will necessitate new interconnect paradigms. In other words, with technology scaling, dependence on traditional materials innovation alone will lead to a brick wall, which only radically different interconnect architectures will enable us to overcome. The conventional 2D copper-based IC is inherently limited because of the planar structure’s geometrical constraints. Innovative interconnect paradigms based on optical technologies, RF and wireless methods, and carbon nanotubes are promising alternatives that may indeed overcome the challenges presented. Although some of these approaches could still be regarded as 2D, they typically offer new degrees of freedom that could have substantial impact on how interconnects are designed and routed, as well as on the delay and power dissipation. In addition to the design and fabrication aspects, other challenges include problems with reliability and development of adequate CAD tools. With technology scaling, the interconnect fabrics will be severely affected by different sources of transient and permanent failures. A big question is how to produce reliable, predictable interconnect architectures from inherently unreliable components. The new interconnect technologies will enable the integration of heterogeneous components (electrical and nonelectrical) in a single SoC. The design of these complex, heterogeneous SoCs will require new simulation and modeling tools. This special issue highlights recent investigations of various revolutionary interconnect paradigms as to whether they can deliver on the promise of greater integration, high performance, good scalability, and high energy efficiency in future SoCs and various other computing platforms. The selected articles represent a wide range of emerging interconnects, from carbon nanotubes, to optical, RF, and on-chip wireless communications. ‘‘Optical Interconnect for High-End Computer Systems,’’ by Ron Ho et al., discusses the use of silicon photonics technology to design large-scale chip Emerging Interconnect Technologies for Gigascale Integration